Field of the Invention
This invention relates to improvements in a cushioning device for cushioning a stack of semiconductor wafers within a wafer transportation container. More particularly, the present cushioning device is a formed or folded ring with compound bends and surfaces that provide variable amounts of cushioning as the compound bends and surfaces engage.
Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
When semiconductor wafers are placed within a transportation container the stack of wafers are either loose or are compressed against the opposing houses. In either case, transportation of the semiconductor wafers can cause abrasion to some or all of the stacked wafers. Some patents have been filed using separator sheets, pads or foam rings to cushion the outer semiconductor wafers and absorb shock and movement as the semiconductor wafers are being transported.
Limiting radial movement becomes an important issue when shipping to prevent abrasion of the prime wafer surface, which may or may not contain circuitry. This is also true for bumped wafers that may or may not be stacked on spacer rings where the rings must only touch the periphery of the wafer and not shift radially into the areas containing the solder bumps. The Wafer Cushioning Rings ability to protect semiconductor wafers is enhanced when using a wafer container that reduces radial wafer shift.
If a rigid spacer is used the spacer can cause harm to the wafers and may not provide sufficient grip on the wafers to prevent movement. If a foam spacer is used the foam spacers are susceptible to damage and aging. Several products and patents have been filed that disclose these features. Exemplary examples of patents covering these products are disclosed herein.
U.S. Pat. No. 3,392,824 issued Jul. 16, 1968 to S. F. Flynn and U.S. Pat. No. 5,366,079 issued Oct. 22, 1994 to Chih-Ching Lin et al., both disclose packaging system for cushioning circuit wafer where the cushioning system is a Bellville type platter or a platter with flexed legs that extend from the center of the platter. While these patents disclose a cushioning system for wafers the cushions slide radially on the outer surface of the wafers as the spacers are crushed within the transportation housing. This can cause damage to the wafers.
U.S. Pat. No. 6,926,150 issued Aug. 9, 2005 to Gonzlo Amador et al., and U.S. Pat. No. 7,530,462 issued May 12, 2009 to Toshitsugu Yajima et al., both disclose a wafer cushion using a rigid disk space. These patents are more related to spacers between the semiconductor wafers rather that providing cushioning and gap filling. In a number of cases these spacers are supplemented with foam pads located either across the entire surface of the wafer or on just the outer edges of the wafer.
U.S. Pat. No. 7,425,362 issued Sep. 16, 2008 to James R. Thomas et al and U.S. Pat. No. 7,611,766 issued to Masahiko Fuyumuro on Nov. 3, 2009 discloses a wavy pad where the high and low parts of the pad fill the space between the wafers and the transportation housing. These pads are made from a variety of materials from plastic to paper and are fabricated in variable profiles to accommodate the space between the wafers and transportation housing.
U.S. Pat. No. 6,926,150 issued Aug. 9, 2005 to Gonzalo Amador et al., U.S. Pat. No. 7,316,312 issued Jan. 8, 2008 to Pei-Liang Chiu and U.S. Patent Application Number 2002/0144927 to Ray G. Brooks et al that published on Oct. 10, 2002 discloses a foam pad or ring to cushion the wafers within the packaging. The amount of force that is applied by a foam pad can be a significant variable as the foam ages. Foams can also be a cause of contamination as the foam cell structure breaks down. Foam particles can also be a contaminant that interferes with the doping of semiconductor wafers. In some cases the foam makes contact with the entire surface of the wafers and can cause deformation of the wafer(s).
What is needed is a cushioning ring that has a variable amount of cushioning to accommodate the minor variation on the top and bottom of a stack of semiconductor wafers. The pending design provides this solution with a single and dual stage wafer cushion.